eax in eax ebx ecx edx 00000000 00000001 68747541 444d4163 69746e65 00000001 00000681 00000000 00000000 0383fbff 80000000 80000008 68747541 444d4163 69746e65 80000001 00000781 00000000 00000000 c1cbfbff 80000002 20444d41 706d6553 286e6f72 20296d74 80000003 30323220 00002b30 00000000 00000000 80000004 00000000 00000000 00000000 00000000 80000005 0408ff08 ff20ff10 40020140 40020140 80000006 00000000 41004100 01008140 00000000 80000007 00000000 00000000 00000000 00000001 80000008 00002022 00000000 00000000 00000000 Vendor ID: "AuthenticAMD"; CPUID level 1 AMD-specific functions Version 00000681: Family: 6 Model: 8 [Duron/Athlon model 8] Standard feature flags 0383fbff: Floating Point Unit Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter (with RDTSC and CR4 disable bit) Model Specific Registers with RDMSR & WRMSR PAE - Page Address Extensions Machine Check Exception COMPXCHG8B Instruction APIC SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions MTRR - Memory Type Range Registers Global paging extension Machine Check Architecture Conditional Move Instruction PAT - Page Attribute Table PSE-36 - Page Size Extensions MMX instructions FXSAVE/FXRSTOR 25 - reserved Generation: 7 Model: 8 Extended feature flags c1cbfbff: Floating Point Unit Virtual Mode Extensions Debugging Extensions Page Size Extensions Time Stamp Counter (with RDTSC and CR4 disable bit) Model Specific Registers with RDMSR & WRMSR PAE - Page Address Extensions Machine Check Exception COMPXCHG8B Instruction APIC SYSCALL/SYSRET or SYSENTER/SYSEXIT instructions MTRR - Memory Type Range Registers Global paging extension Machine Check Architecture Conditional Move Instruction PAT - Page Attribute Table PSE-36 - Page Size Extensions 19 - reserved AMD MMX Instruction Extensions MMX instructions FXSAVE/FXRSTOR 3DNow! Instruction Extensions 3DNow instructions Processor name string: AMD Sempron(tm) 2200+ L1 Cache Information: 2/4-MB Pages: Data TLB: associativity 4-way #entries 8 Instruction TLB: associativity 255-way #entries 8 4-KB Pages: Data TLB: associativity 255-way #entries 32 Instruction TLB: associativity 255-way #entries 16 L1 Data cache: size 64 KB associativity 2-way lines per tag 1 line size 64 L1 Instruction cache: size 64 KB associativity 2-way lines per tag 1 line size 64 L2 Cache Information: 2/4-MB Pages: Data TLB: associativity L2 off #entries 0 Instruction TLB: associativity L2 off #entries 0 4-KB Pages: Data TLB: associativity Direct mapped #entries 0 Instruction TLB: associativity Direct mapped #entries 0 size 1 KB associativity L2 off lines per tag 129 line size 64 Advanced Power Management Feature Flags Has temperature sensing diode Maximum linear address: 32; maximum phys address 34